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Texas Instruments /MSP432P4011 /SystemControlSpace /MVFR0

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Interpret as MVFR0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0A_SIMD_REGISTERS 0SINGLE_PRECISION 0DOUBLE_PRECISION 0FP_EXCEPTION_TRAPPING 0DIVIDE0SQUARE_ROOT 0SHORT_VECTORS 0FP_ROUNDING_MODES

Description

Media and FP Feature Register 0 (MVFR0)

Fields

A_SIMD_REGISTERS

Indicates the size of the FP register bank. The value of this field is: 0b0001 - supported, 16 x 64-bit registers.
SINGLE_PRECISION

Indicates the hardware support for FP single-precision operations. The value of this field is: 0b0010 - supported.
DOUBLE_PRECISION

Indicates the hardware support for FP double-precision operations. The value of this field is: 0b0000 - not supported in ARMv7-M.
FP_EXCEPTION_TRAPPING

Indicates whether the FP hardware implementation supports exception trapping. The value of this field is: 0b0000 - not supported in ARMv7-M.
DIVIDE

Indicates the hardware support for FP divide operations. The value of this field is: 0b0001 - supported.
SQUARE_ROOT

Indicates the hardware support for FP square root operations. The value of this field is: 0b0001 - supported.
SHORT_VECTORS

Indicates the hardware support for FP short vectors. The value of this field is: 0b0000 - not supported in ARMv7-M.
FP_ROUNDING_MODES

Indicates the rounding modes supported by the FP floating-point hardware. The value of this field is: 0b0001 - all rounding modes supported.

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data